Session A: Advanced Computer Architecture and Hardware Synthesis

3 September 2026, 10:10-11:10

Title
Cutting DRAM Refresh Energy with Bank-Granular Rowhammer Mitigation Jeeho Ryoo (Fairleigh Dickinson University, Canada); Patrick Stockton (University of Texas at San Antonio, USA); Cory Davis (University of Texas at San Antonio, USA); Marco Ho (British Columbia Institution of Technology, Canada); Michael Hsiao (Virginia Tech, USA); Eugene B. John (University of Texas at San Antonio, USA) As DRAM density scales, refresh energy constitutes an increasingly dominant share of total memory power, and Rowhammer mitigations compound this cost by issuing rank-wide preventive refreshes that block all banks indiscriminately- even when only a small subset contains rows at risk. This energy overhead stems from a missing interface: DDR5’s rank-level alert mechanism does not expose which bank triggered the alert, forcing the memory controller to default to all-bank refresh. We propose Selective-Bank Refresh (SBR), the first mechanism to expose per-bank PRAC criticality status to the memory controller, enabling energy-proportional preventive refresh using existing DDR5 command primitives. SBR encodes bank-level Per-Row Activation Counting (PRAC) status in a lightweight bitmap mapped to reserved JEDEC mode-register bits, requiring only minimal additional state and control logic. The controller reads this bitmap via a standard Mode Register Read (MRR) and issues RFMsb exclusively to critical banks, replacing rank-wide preventive refresh with precisely targeted same-bank operations. Across 56 workloads and adversarial attack traces, SBR reduces redundant preventive refreshes by up to 63.1%, lowers DRAM energy by 27.8% on average (up to 42.6%), and improves system performance by 3.2% on average (up to 12.6%) over conventional all-bank refresh, while maintaining the memory system from Rowhammer vulnerabilities.
ParaYosys: Tail-Aware Partition-Based Parallel RTL Synthesis Zhengyi Zhang (Fudan University, China); Sijing Yang (Fudan University, China); Lingli Wang (Fudan University, China) Open-source RTL synthesis still underuses multicore machines because backend optimization mixes local rewriting with global transformations. We present ParaYosys, a partition-based parallel RTL synthesis framework implemented inside Yosys. ParaYosys partitions flattened RTL, exports deterministic partition netlists, runs partition-local backends in worker processes, and stitches legal whole-design netlists. Under a post-flatten backend-only scope, a 24-partition configuration completes 22 of 23 public RTL benchmarks, reaches 5.96x speedup, and gives 1.38x median speedup. Larger public designs up to 483,682 flattened cells still reach 3.18x-5.37x. The main finding is that structural balance poorly predicts backend cost: the median structural tail is 1.04x, the median runtime tail is 5.34x, and the worst per-benchmark cost-model gap is 352x. Lightweight partition features improve critical-shard identification from 9.1% to 45.5%, and cost-aware weighting reduces parallel wall time on 8 of 10 controlled reruns. Successful P24 cases pass CEC, with small median mapped QoR drift.
MPTAC: Memory Controller Partitioning and Traffic-Aware Contention Control in GPUs Vahid Geraeinejad (KTH Royal Institute of Technology, Sweden); Paul Delestrac (KTH Royal Institute of Technology, Sweden); Javier Barrera (Barcelona Supercomputing Center (BSC), Spain); Francisco J. Cazorla (Barcelona Supercomputing Center (BSC), Spain); Masoumeh Ebrahimi (KTH Royal Institute of Technology, Sweden); Ahmed Hemani (KTH Royal Institute of Technology, Sweden) The advent of cloud-based artificial intelligence and the increased digitalization of embedded systems require powerful GPUs capable of simultaneously running kernels from different software providers. To accommodate the resource isolation and Execution Time Determinism (ETD) needed with the increasing number of kernels running simultaneously, modern NVIDIA GPUs implement MIG (Multi-Instance GPU) that effectively partitions GPU resources among kernels. However, current trends show that more kernels than the available GPU partitions need to be executed simultaneously, hence, requiring that several kernels share the same GPU partition. In this work, we show that current solutions for GPU resource partitioning fail to prevent kernels running in the same partition from affecting each other’s performance. We identify the request buffers in the GPU’s network-on-chip and memory controller as the main sources of this contention and propose a low-overhead mechanism, MPTAC, to monitor and control it. MPTAC partitions request buffers and introduces a software-configurable threshold parameter to enable flexible Quality-of-Service (QoS), choosing between high kernel isolation when needed for critical kernels and balanced isolation performance otherwise. MPTAC is evaluated using both synthetic workloads and representative benchmarks. In the most aggressive cases, it successfully reduces contention in the GPU partition, bringing the slowdown of the analysis kernel from 3.83× to 1.43× in synthetic workloads, and from 2.35× to a more manageable 1.78× in representative benchmarks.

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Session B: Custom Instruction-Set and Vector Accelerators

3 September 2026, 11:40-12:40

Title
High-Throughput Interleaved QRD for FPGAs Bogdan Pasca (Altera Corporation, France); Yohann Uguen (Altera Corporation, France); Martin Langhammer (Altera Corporation, United Kingdom) Floating-point QRD implementations on FPGAs can achieve high throughput when the latency of the compute datapath is small relative to the matrix dimension, as is often the case for large single-precision matrices on hard FP-enabled devices. However, throughput and hardware utilization degrade sharply when this balance is unfavorable. In such latency-dominated configurations, loop-carried dependencies introduce many pipeline bubbles, and the hardware may spend most cycles idle. In this work, we propose an interleaved QRD schedule based on the modified Gram-Schmidt algorithm that reuses these otherwise idle cycles to process independent decompositions on the same datapath. The proposed schedule preserves the baseline computation while requiring only limited additional state and control logic. Experimental results on Agilex 7 show throughput improvements of up to 3.7X, with less than 5% additional logic in several configurations and, in some cases, no increase in DSP or memory-block usage.
Real-Time MIMO MMSE Equalization Using Standard RISC-V Vector Extensions Zexu Tan (Technische Universität Dresden, Germany); Sheikh Faizan Qureshi (Technische Universität Dresden, Germany); Emil Matus (Technische Universität Dresden, Germany); Dmitry Utyansky (Synopsys, Inc., USA); Pieter van der Wolf (Synopsys, Inc., USA); Gerhard Fettweis (Technische Universität Dresden, Germany) The evolution of 5G New Radio (NR) increases the demand for flexible, portable, software-based baseband processing on programmable platforms. However, current solutions are still largely based on highly specialized DSPs or FPGAs, which often require dedicated tool flows and offer limited portability. The recently ratified RISC-V vector extension (RVV 1.0) provides an open-standard vector ISA that may address these limitations. Still, its suitability for wireless baseband workloads remains unclear due to the absence of DSP-specific and complex-arithmetic instructions. This paper investigates the feasibility of implementing an MMSE-based MIMO equalizer for OFDM systems using standard RVV 1.0 instructions and 32-bit fixed-point arithmetic. We present a methodology that combines BER (Bit Error Rate)-driven precision selection, subcarrier-parallel vectorization, register-pressure management, and instruction rescheduling. Using a 4×4 OFDM-MIMO system as a case study, our implementation on Saturn with VLEN = 4096 bits and DLEN = 512 bits/cycle achieves a 100× speedup over its scalar baseline and a throughput of 28.05 cycles per symbol while maintaining BER performance comparable to the floating-point reference under the evaluated conditions. We further estimate the processor-frequency requirements for representative LTE and 5G scenarios and compare the results across the RVV processors Ara2 and Saturn. The study identifies both the capabilities and the limitations of standard RVV 1.0 for wireless baseband processing and highlights promising directions for future ISA and microarchitectural enhancements.
CIA: Composable Instruction-Based Accelerators Brandon Freiberger (UBC, Canada); Joseph Maheshe (UBC, Canada); Jan Gray (Gray Research LLC, WA); Guy Lemieux (UBC, Canada) The use of custom instructions is a common approach to accelerate domain-specific problems. However, it is difficult to reuse instruction-based accelerators in new systems – for example, if multiple accelerators from past systems are merged into a single SoC, they may have colliding opcodes. Fixing this requires opcode reassignment (assuming this is possible), and all software needs to be recompiled. From this perspective, custom instruction-based accelerators are not portable and are therefore difficult to re-use. Another problem with such accelerators is providing OS-level access control and virtualization. While it is easy to make an accelerator exclusive to one process, it is challenging to share an accelerator in a multicore + multiprogrammed environment. Composable Instruction-based Accelerators, or CIA, solves these problems. First, it enables composability, where separately authored instruction-based accelerators can be merged into any future SoC and binary compatibility of software is maintained without recompilation. Second, it virtualizes the accelerator state, allowing multiple processes to share an accelerator while maintaining fully isolated state contexts under OS management. Through universal context save and restore that works with any accelerator, the OS provides access control and virtualized state management in multicore and multiprogrammed environments. The commercial impact is profound: CIA enables a marketplace of distinct Accelerator IP Vendors, who are domain experts, CPU Vendors, and SoC Vendors who create systems with arbitrary mixes of accelerators. CIA allows all hardware instances to execute the same software binaries, regardless of accelerator composition. This paper presents a case study, demonstrating how to deploy CIA into the RISC-V environment, yielding speedups through latency hiding, by switching between multiple accelerator contexts, and replication of accelerator units.

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Session C: FPGA Design Automation Frameworks

3 September 2026, 15:00-15:45

Title
A Synthetic Benchmark Generator for Evaluating FPGA Incremental Tools Elmira Nezamfar (University of British Columbia, Canada); Steven J.E. Wilton (University of British Columbia, Canada) Incremental compilation has emerged as a popular methodology in FPGA design to shorten design cycles. Developing new incremental design tools and algorithms requires a set of benchmark circuits to evaluate proposed ideas. Although many benchmark suites are suitable for evaluating FPGA CAD, none are appropriate for evaluating incremental design flows since none contain a history of each design. This paper addresses this gap by introducing a framework for generating a synthetic history for real circuits. Our approach is to start with real designs and remove parts of the design incrementally, creating a “history” of a design that is intended to mimic designer behaviour. We present an open-source benchmark generation framework that integrates with RapidWright. Our method formulates this problem as an optimization problem in which the generation of synthetic design histories can be controlled by the user through specifying the amount of removal from the source design. We generated more than 150 synthetic benchmarks across standard VTR circuits [3], Koios [2], and open-source designs like cva5 [1]. All the synthetic benchmarks can be used within Vivado’s incremental flow, demonstrating that the generated benchmarks are synthesizable, effective, and well-suited for evaluating incremental FPGA tools.
FQTree: Fine-Grained Quantization and Hardware Generation of Boosted Decision Trees Zhiqiang Que (University of Bristol, UK); Chang Sun (California Institute of Technology, USA); Haiyang Wang (California Institute of Technology, USA); Dinesh Pamunuwa (University of Bristol, UK); Roshan Weerasekera (University of Bristol, UK); Qijia Tang (University of Bristol, UK); Bakhtiar Zadeh (Imperial College London, UK); Wayne Luk (Imperial College London, UK); Maria Spiropulu (California Institute of Technology, USA) Boosted decision trees (BDTs) are widely used in latency-critical applications, but efficient hardware deployment remains challenging. Existing designs often rely on uniform or manually tuned fixed-point formats, which can introduce unnecessary hardware cost or accuracy loss. This work presents the FQTree algorithm https://github.com/ecs-bristol/FQTree for fine-grained quantization-aware training of BDTs, together with the QXGB framework for automatic hardware generation. FQTree introduces a hardware-oriented leaf-value quantization scheme that uses a global quantization step together with a tree-wise shift, enabling compact non-negative integer leaf representations, controlled clipping/pruning, and bias folding to reduce datapath cost. This work further applies this quantization during boosting so that later trees adapt to the errors of the already-quantized ensemble, and then lowers the trained model into low-latency hardware implementations through a compiler-based flow. Results on JSC, MNIST, and NID show that our method reduces LUT usage by 26-57% compared with the state-of-the-art FPGA-based BDT designs while matching or improving accuracy.
RH+: Row-Hit-Optimized Scheduling for PIM-Based LLM Inference (short paper) Yongchan Jung (Fairleigh Dickinson University, Canada); Shafayat Mowla Anik (University of Colorado Colorado Springs, USA); Byeong Kil Lee (University of Colorado Colorado Springs, USA); Jeeho Ryoo (Fairleigh Dickinson University, Canada) Large language model inference on processing-in-memory (PIM) architectures promises to break the memory wall by performing multiply-accumulate (MAC) operations directly within HBM3 DRAM banks. Prior work identifies the power constraint timing parameter nCCDAB as the primary performance bottleneck and optimizes scheduling accordingly. We demonstrate that for GEMV operations that dominate autoregressive decoding, the DRAM row cycle time (nRC) is 10 to 11 times larger than nCCDAB. Consequently, nCCDAB is entirely masked, rendering prior nCCDAB-focused optimizations ineffective for these workloads. The root cause is inherited host-centric address interleaving, which forces every all-bank MAC command into a different DRAM row. We propose RH+ scheduling, a simple stride change that keeps 32 consecutive MAC operations within the same row. Cycle-accurate simulation across four LLM workloads shows that RH+ delivers 8-12x speedup, over 74% energy reduction, and up to 52x EDP improvement.

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Session D: Emerging and Uncoventional Applications

4 September 2026, 10:00-11:00

Title
SCU: An SFQ Co-Design for Bit-Vector Approximate Matching in Genome Alignment Peiyao Qu (Institute of Computing Technology, Chinese Academy of Sciences, China; University of Chinese Academy of Sciences, Chin); Haihang You (Institute of Computing Technology, Chinese Academy of Sciences, China); Guangming Tang (Institute of Computing Technology, Chinese Academy of Sciences, China) Genome alignment is a fundamental genomics workload that demands both high throughput and high energy efficiency, yet the applicability of Single-Flux-Quantum (SFQ) logic to this domain remains unclear. We present SCU, a superconducting computing unit for the regular Bitap-style bit-vector state-update kernel used in approximate matching. SCU reformulates this kernel for SFQ-friendly execution and maps it onto a stage-structured microarchitecture with two design points: a throughput-oriented Baseline SCU and an implementation-cost-oriented Stage-Reused SCU. We physically implement and verify 4-bit RSFQ SCU variants, extract layout-level area and Josephson-junction (JJ) counts, and use the demonstrator to calibrate width-scaled, replicated-core projection. Under a 64-bit/64-core kernel model, the RSFQ-calibrated SCU projection achieves up to 16.6x higher throughput than a baseline derived from the published GenASM-DC kernel formulation under the same configuration. Overall, the results show that representative approximate-matching computation can be effectively mapped to pulse-based, deeply pipelined SFQ hardware, while stage reuse exposes an SFQ-specific throughput-cost tradeoff.
Efficient Circuit Management and Scheduling in Multi-Node Quantum Systems with Dynamic Links Zefan Du (Fordham University, USA); Wenrui Zhang (New Jersey Institute of Technology, USA); Jake Gesseck (Fordham University, USA); Wenqi Wei (Fordham University, USA); Juntao Chen (Fordham University, USA); Tao Han (New Jersey Institute of Technology, USA); Zhiding Liang (Rensselaer Polytechnic Institute, USA); Ying Mao (Fordham University, USA) The realization of practical quantum advantage requires executing large-scale circuits that far exceed the qubit capacity of any single quantum processor. To address this, two primary scaling strategies have emerged: circuit cutting, which utilizes classical resources to decompose circuits into smaller fragments, and multi-node networking, which uses quantum resources like EPR pairs to link hardware. However, these methods present a critical trade-off: circuit cutting incurs a classical reconstruction overhead that grows exponentially as O(4K) with the number of cuts K, while EPR-based communication introduces significantly higher noise than local operations, degrading overall fidelity. We present ECLIPSE (Efficient Circuit Management and Link-aware Interconnect Placement and Scheduling for large-scale circuit Execution), a unified framework for multi-node quantum systems. ECLIPSE jointly optimizes circuit partitioning, EPR-pair allocation, noise-aware scheduling, and execution by analyzing the connectivity and gate structure of the input circuit to balance classical sampling overhead against quantum communication noise. ECLIPSE comprises: (1) a Circuit Analyst that identifies subcircuit pairs whose EPR based merging yields a large reduction in sampling overhead; (2) a System Reconfiguration module that assigns each EPR link to a low-noise physical worker pair; and (3) a Scheduler that distributes subcircuits to workers to reduce cumulative noise impact. We implement ECLIPSE using IBM Qiskit and Quantinuum Pytket and evaluate it on real quantum hardware and multiple emulators. Across these platforms, ECLIPSE outperforms state-of-the-art Qiskit-Addon-Cut by up to 16.7% in multi-node fidelity and 40.8% for deep circuits at high EPR success rates, while reducing cumulative overhead by up to 99.5% at 8 workers, thereby enabling practical large-circuit execution on today’s distributed quantum systems.
Ouros: A Dataflow-Driven Processor for Lazy Functional Programming Languages Yukang Xie (Heriot-Watt University, UK); Craig Ramsay (Heriot-Watt University, UK); Robert Stewart (Heriot-Watt University, UK); Hans-Wolfgang Loidl (Heriot-Watt University, UK) This paper presents Ouros, a pipelined processor for lazy functional programming languages based on combinator graph reduction. Ouros overcomes the inherent sequentiality of graph reduction through dataflow-driven execution and automatic fine-grained multi-threading. It maintains pipeline utilisation by hiding per-thread latency and interleaving multiple independent threads. Its concurrent garbage collector (GC) addresses the high memory allocation pressure of functional language execution. The correctness of the GC algorithm is verified via model checking. Ouros achieves a higher clock frequency than the single-cycle KappaMutor processor in FPGA implementation, and is faster by 20.9% on average across 10 Haskell benchmarks (up to 118% on richly-threaded programs). GC overhead ranges from 0% to 23% depending on program allocation behaviour.

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Session E: Reconfigurable Processor Arrays and Approximate Computing

4 September 2026, 11:30-12:30

Title
Zero-Overhead Loop Control for Tightly Coupled Processor Arrays (TCPAs) Dominik Walter (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany); Frank Hannig (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany); Jürgen Teich (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany) Multidimensional loop kernels often suffer from control overhead that can dominate execution time on parallel loop accelerators. Tightly Coupled Processor Arrays (TCPAs) offload loop control to a Global Controller (GC), but existing approaches still require hundreds of control signals. We propose a method to derive and aggressively reduce these control conditions from a polyhedral representation of the iteration space, achieving reductions of 15 x to 45 x in control signals across several benchmarks. We introduce a lightweight GC architecture that evaluates conditions as unions of polyhedra using bounded evaluation units, requiring hardware comparable to a single processing element. Control signals are distributed throughout the array with a minimal number of delay elements resulting in zero-overhead loop control. Our evaluation on PolyBench kernels shows that the entire control flow requires 10 % of the total array resources.
Symbolic Energy Analysis for Nested Loop Accelerators Avinash Mahesh Nirmala (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany); Dominik Walter (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany); Frank Hannig (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany); Jürgen Teich (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany) This work presents a symbolic approach for estimating the energy consumption for nested loop programs when mapped and scheduled on parallel processor array accelerator architectures. Instead of simulation-based evaluation, we derive a methodology for symbolic energy analysis that captures the impact of mapping and scheduling decisions of loop nests on processor arrays. We compare our approach against simulation-based results for selected benchmarks and varying sizes of the iteration spaces. Whereas the latter are not scalable, our symbolic analysis is shown to be independent of the problem size. The presented evaluation methodology can be beneficially used during the design space exploration of mapping and scheduling decisions, for studying the influence of array size variations, and for comparisons with other loop nest accelerator architectures.
VAHANA: Hardware-Aware Noise Addition Against Gradient Inversion Attacks Arsalan Ali Malik (North Carolina State University); Digvijay Anand (North Carolina State University); Chau-Wai Wong (North Carolina State University); Aydin Aysu (North Carolina State University) Federated learning (FL) enables clients to collaboratively train a global model by sharing gradient updates instead of raw data. However, recent studies show that these shared gradients can be exploited to reconstruct private training data through gradient inversion attacks, posing a serious threat to client privacy. A common defense strategy is gradient obfuscation, which perturbs gradients before transmission; however, it relies on costly hardware components, such as Gaussian samplers and floating-point (FP) multipliers, making it unsuitable for resource-constrained edge devices. Approximate circuits-extensively studied in computer architecture and VLSI for their energy, area, and latency benefits-offer a promising defense. Yet despite its success in machine learning accelerators, it remains underexplored for privacy-preserving FL. This work introduces variational approximate hardware-aware noise addition (VAHANA), a hardware-efficient method that integrates stochastic perturbations directly into the computation using approximate circuits and only 4 bits of uniform randomness, eliminating the need for Gaussian sampling or FP multiplication. We integrate VAHANA into the open-source RISC-V CV32E40P softcore using a hardware-software co-design approach, implementing custom instruction extensions that accelerate privacy-preserving operations with improved execution efficiency in both time and area. Evaluation on the Kintex-7 FPGA shows that VAHANA reduces memory footprint by 34% and reduces latency by up to 28.1×, while maintaining resilience against gradient inversion attacks on Medical MNIST, CIFAR-10, and CIFAR-100 datasets.

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Session F: Reliable and Efficient Reconfigurable Computing

4 September 2026, 14:00-15:00

Title
FT-CGRA: Compiler-Transparent Fault Tolerance for CGRAs Ensieh Aliagha (Technische Universität Dresden, Germany); Vijaya Shangamesh Manoharan Amutha (Technische Universität Dresden, Germany); Diana Göhringer (Technische Universität Dresden, Germany) Coarse-grained reconfigurable architectures (CGRAs) promise high energy efficiency but remain vulnerable to transient upsets and aging-induced defects. We introduce a compiler-transparent reliability framework that provides online error detection and fast in-field recovery without requiring remapping or software checkpoints. The proposed approach distinguishes transient from permanent faults at runtime and enables rapid handover to healthy resources with low performance overhead. Experimental results demonstrate competitive fault coverage, bounded recovery latency, and negligible impact on steady-state throughput. In addition, a mean time to failure (MTTF) improvement of more than 2.5× is achieved over the baseline without fault tolerance.
PASTE: A Physical-Aware Surrogate for FPGA Pre-Routing Timing Estimation Yunfei Dai (Fudan University, China); Kaixiang Zhu (Fudan University, China); Mingyang Chen (Fudan University, China); Lingli Wang (Fudan University, China) Accurate pre-routing timing estimation is a fundamental challenge in FPGA design, since the final path delay is jointly determined by the timing graph, the placement, and the architecture-constrained routing fabric. Existing methods target only coarse-grained proxies, rather than fine-grained node-level arrival-time prediction. In this paper, we present PASTE, a physical-aware surrogate for FPGA pre-routing timing estimation. PASTE constructs physically informative features on the post-placement timing graph, including the placement geometry, the post-placement timing prior, and routing-density signals derived from a design-aware pruned routing resource graph. Building on these features, we propose the Timing Propagation Network (TPN), a two-stage graph neural network that jointly predicts node-level arrival times and critical path delay. Stage I uses heterogeneous message passing to learn local multi-type timing dependencies, while Stage II performs edge-gated max propagation to model the long-range max-plus accumulation underlying static timing analysis. Both stages operate directly on the timing graph without explicit per-net routing-aware modeling, improving scalability to large designs while enabling sub-second inference. Implemented in VTR, PASTE achieves a node-level MAPE of 8.48% and a graph-level CPD MAPE of 8.28% under the circuit-level setting on the test set. As a downstream validation, integrating PASTE into a predictor-guided retiming flow achieves an average F_max improvement of 30.83% over the unoptimized baseline, outperforming logic-only ABC retiming by 2.36 percentage points. These results demonstrate that PASTE serves as an effective timing surrogate for early-stage timing analysis and timing-driven FPGA optimization.
ADAD: An Energy-Efficient Hardware Solution for Real-Time Anomaly Detection Using Extended Decorrelation-Based Method Amirhossein Sadough (Radboud University, The Netherlands); Mahyar Shahsavari (Radboud University, The Netherlands); Mark Wijtvliet (ASMPT, The Netherlands); Marcel van Gerven (Radboud University, The Netherlands) This paper presents ADAD, an energy-efficient hardware solution for real-time streaming anomaly detection built on an extended decorrelation-based algorithm (EDAD). EDAD extends a prior decorrelation-based anomaly detector, which operates in a continual-updating regime suited for non-stationary environments, with a Freeze-After-Learn regime for stationary environments where only background data is available. EDAD yield a unified algorithm covering both stationary and non-stationary environments while operating strictly sample-wise, making it well suited for streaming deployment. Application agnosticism is validated across two different benchmarks. On the LHC physics dataset, EDAD outperforms two autoencoder-based baselines on three of four detection tasks. On nine widely-used ODDS benchmark datasets spanning healthcare, image, astronautics, and linguistics domains, EDAD achieves the highest average AUC of 0.879 among four established detectors. ADAD realizes both EDAD regimes in a unified scalable architecture, supporting up to 512 feature dimensions. FPGA-based ADAD implementation delivers substantial energy efficiency gains over general-purpose platforms, up to 1587× over CPU and 3514× over GPU. It also achieves 1.8× lower energy per sample and higher AUC versus prior FPGA-based anomaly detectors. The 45~nm ASIC implementation achieves pico-joule per operation across feature dimensions, offering a practical application-agnostic solution for energy-efficient edge AD and system-level integration.

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Session G: Short Papers

4 September 2026, 16:45-17:05

Title
QXL – A Scalable Hardware Framework for Tabular Q-Learning Inference on RISC-V Krishna R. Chinmay (International Institute of Information Technology Bangalore, India); Pruthvi Parate (International Institute of Information Technology Bangalore, India); Pavan K. Phani (International Institute of Information Technology Bangalore, India); Madhav Rao (International Institute of Information Technology Bangalore, India) Tabular Q-learning is a foundational reinforcement learning (RL) algorithm used in embedded decision-making, yet its inference phase suffers from latency-sensitive memory accesses, creating severe bottlenecks in real-time control systems. To address this, we present QXL, a hardware-software co-designed inference accelerator, seamlessly integrated as a custom instruction extension for RISC-V processors. Rather than employing complex, power-hungry dynamic caches, QXL utilizes an on-chip firmware profiling routine to track state visitation. The optimal actions for these high-traffic states are pre-loaded into a lightweight, configurable register scratchpad, bypassing main memory lookups during inference. We evaluate the framework’s versatility across three diverse embedded domains: adaptive traffic signal control, stochastic inventory management, and spatial pathfinding. Hardware synthesis on a Nexys FPGA and a 45 nm ASIC demonstrates that QXL’s internal datapath decouples from state-space complexity, allowing the logic to scale logarithmically in area. By successfully offloading the decision-making loop, QXL achieves up to a 60% reduction in inference cycle count and a 3.09× improvement in execution efficiency, establishing a deterministic, low-power architecture for real-time edge RL applications.
Towards Efficient Matrix Operations on CGRAs with Linear Computation Coding Dataflows Florian Rokohl (University of Rostock, Germany); Alex Lehnert (University of Rostock, Germany); Marc Reichenbach (University of Rostock, Germany) CGRAs can improve deep neural network inference performance over TPU architectures. They share a similar dataflow style of execution, but their routing networks are reconfigurable and thus flexible. State-of-the-art CGRA mapping tools, however, target control-flow abstractions and therefore do not fully exploit this reconfigurable routing. We show that dataflow approaches to constant matrix-vector multiplications, which already achieve high throughput on FPGAs, also improve CGRA performance. The resulting mappings reach speedups of up to 4.4× over conventional Mul+Add CGRA mappings and 2.3× over a systolic-array lower bound, while substantially reducing memory intensity.
When Timing is Uncertain, Infer: Probabilistic Early FPGA Timing Analysis for Robust Critical Path Optimization Omar Sharif (Imperial College London, UK); Filip Wojcicki (Imperial College London, UK); Tarik Ourida (Imperial College London, UK); Wayne Luk (Imperial College London, UK); Christos-Savvas Bouganis (Imperial College London, UK) Early-stage FPGA timing analysis is inherently uncertain: routing is incomplete, congestion is only partially observed, and interconnect delays are coarsely estimated. Despite this, timing-driven placement relies on deterministic static timing analysis (STA), whose max-based propagation enforces hard path selection and discards competing near-critical paths. We replace this propagation with a probabilistic formulation that models arrival times as random variables and approximates max operations using Gaussian moment matching, preserving multi-path competition. Integrated into VTR as a drop-in timing evaluation layer, the method requires no modification to the placement algorithm and remains compatible with existing optimizers. Across the VTR 7.0 benchmark suite, the method achieves a 6.05% geometric-mean reduction in critical path delay (CPD), reduces seed-dependent CPD variation by 60.9%, and incurs a 5.11% total-flow runtime overhead.
BenDi: An Energy-Efficient Quasi-Stochastic Systolic Architecture for Edge Bioelectronics Bochen Ye (The University of Edinburgh, United Kingdom); Yihan Pan (The University of Edinburgh, Edinburgh, United Kingdom); Shady Agwa (The University of Edinburgh, Edinburgh, United Kingdom); Themis Prodromakis (The University of Edinburgh, Edinburgh, United Kingdom) Continuous long-term monitoring and diagnosis of biomedical signals, such as electrocardiograms (ECGs), can help mitigate an increasing threat to public health. Artificial Intelligence (AI) models, such as Convolutional Neural Networks (CNNs), provide accurate monitoring and classification for relevant diseases; however, they require more computational resources than conventional AI hardware can typically afford, especially for a resource-constrained environment on the edge. In this work, we present BenDi, an energy-efficient quasi-stochastic systolic architecture for bioelectronic systems on the edge. BenDi leverages multiple levels of energy and power optimization, ranging from circuits to software quantization, including low supply voltage, the Bent-Pyramid data format for quasi-stochastic multiplication, the DiP systolic dataflow, and hardware-aware quantization, to handle CNNs with high accuracy on the edge within limited hardware budgets. The hardware implementation results, using a commercial 22nm technology, show that BenDi architecture, at 0.5 Voltage and 100 MHz, offers 3.35x smaller area and 5x higher energy efficiency, compared to state-of-the-art binary-based weight-stationary systolic architectures. Regarding Bioelectronic edge systems, BenDi achieves an order-of-magnitude improvement in energy efficiency and another order-of-magnitude improvement in area efficiency, compared to its counterparts. This significant improvement comes at the cost of 1% to 3.3% accuracy loss on the MIT-BIH and Apnea-ECG benchmarks, respectively, compared with conventional computing using the 32-bit floating-point format.

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Posters

3 September 2026, 12:40-14:00

Bridging the DSP Gap: A Streamed, Multiplier-Less Edge AI Operator via Logarithmic Co-Design
Changyan Liu (University of Electronic Science and Technology of China, China); Ming Xiao (University of Electronic Science and Technology of China, China); Shasha Feng (University of Electronic Science and Technology of China, China)

CPU-Power Optimization in Harsh Environments Using Temperature-Aware Scheduling
Nico Rumpeltin (Leibniz University Hanover, Germany); Tim-Marek Thomas (Leibniz University Hanover, Germany); Malte Rücker (Drilling Services, Baker Hughes, Germany); Malte Hawich (Leibniz University Hanover, Germany); Daniel Lohmann (Leibniz University Hanover, Germany); Holger Blume (Leibniz University Hanover, Germany)

Memory-Aware Architectural Exploration Method to Design Programmable Multi-Core Accelerators
Chanon Khongprasongsiri (Université Bretagne Sud, France); Philippe Tanguy (Université Bretagne Sud, France); Kevin J. M. Martin (Université Bretagne Sud, France); Philippe Coussy (Université de Bretagne-Sud, France)

Pattern Analysis of Pruned Convolutional Kernels for Computation Skipping in Variable-Parallelism Reconfigurable Architecture
Yu Inoue (Hokkaido University, Japan); Atsushi Hori (Hokkaido University, Japan); Takao Marukame (Hokkaido University, Japan); Tetsuya Asai (Hokkaido University, Japan); Alexandre Schmid (Swiss Federal Institute of Technology in Lausanne, Switzerland); Kota Ando (Hokkaido University, Japan)

Safety-Critical Deadline Compliant Static Task Scheduling for Heterogeneous Architectures
Jonas Hollmann (Leibniz University Hanover, Germany); Jakob Arndt (Infineon Germany, Germany); Holger Blume (Leibniz University Hanover, Germany)

RH+: Row-Hit-Optimized Scheduling for PIM-Based LLM Inference (short paper)
Yongchan Jung (Fairleigh Dickinson University, Canada); Shafayat Mowla Anik (University of Colorado Colorado Springs, USA); Byeong Kil Lee (University of Colorado Colorado Springs, USA); Jeeho Ryoo (Fairleigh Dickinson University, Canada)

3 September 2026, 15:45-16:40

Forward-Mode Automatic Differentiation for the RISC-V RV32IMF Instruction Set
Johannes Schoder (Friedrich Schiller University Jena, Germany); H. Martin Bücker (Friedrich Schiller University Jena, Germany)

A Near-Cache RISC-V Coprocessor for Efficient Posit Dot-Product Acceleration
Nico Röder (Chair of Adaptive Dynamic Systems, Technische Universität Dresden, Germany); Ahmed Kamaleldin (Chair of Adaptive Dynamic Systems, Technische Universität Dresden, Germany); Diana Göhringer (Chair of Adaptive Dynamic Systems, Technische Universität Dresden, Germany)

Design in Tiles: Automating GEMM Deployment on Tile-Based Many-PE Accelerators
Aofeng Shen (ETH Zürich, Switzerland); Chi Zhang (ETH Zürich, Switzerland); Yakup Budanaz (ETH Zürich, Switzerland); Alexandru Calotoiu (ETH Zürich, Switzerland); Bowen Wang (ETH Zürich, Switzerland); Torsten Hoefler (ETH Zürich, Switzerland); Luca Benini (ETH Zürich, Switzerland)

Generation of Scalar ASIPs with OpenVADL
Linus Halder (Technische Universität Wien, Austria); Matthias Raschhofer (Technische Universität Wien, Austria); Andreas Krall (Technische Universität Wien, Austria)

NanoLogicController: A Minimal Open-Source ASIP for Accelerated Gate-Level Netlist Emulation
Moritz Weissbrich (TU Braunschweig, Germany); Mohamed Wassim Chebili (TU Braunschweig, Germany); Guillermo Payá-Vayá (TU Braunschweig, Germany)

WS-RPE: A Hardware Work-Stealing Scheduler with Redundant-PE Activation for Real-Time Eigenvalue Computation in Edge Physics-AI
Jiyuan Miao (Beijing University of Chemical Technology, Chin); Hongfang Yuan (Beijing University of Chemical Technology, Chin); Xi Cao (Beijing University of Chemical Technology, China)

4 September 2026, 12:40-14:00

QXL – A Scalable Hardware Framework for Tabular Q-learning Inference on RISC-V (short paper)
Chinmay Krishna R (International Institute of Information Technology Bangalore); Pruthvi Parate, Phani Pavan Kambhampati (MS Research Student, VLSI and Embedded Systems, IIIT Bangalore); Madhav Rao (IIIT Bangalore)

Towards Efficient Matrix Operations on CGRAs with Linear Computation Coding Dataflows (short paper)
Florian Rokohl, Alexander Lehnert, Marc Reichenbach (Institute of Applied Microelectronics and Computer Engineering, University of Rostock)

When Timing is Uncertain, Infer: Probabilistic Early FPGA Timing Analysis for Robust Critical Path Optimization (short paper)
Omar Sharif, Filip Wojcicki, Tarik Ourida, Wayne Luk (Imperial College London); Christos-Savvas Bouganis (Imperial College London, UK)

BenDi: An Energy-Efficient Quasi-Stochastic Systolic Architecture for Edge Bioelectronics (short paper)
Bochen Ye, Yihan Pan, Shady Agwa, Themis Prodromakis (University of Edinburgh)

Shared Load-Store Unit for Instruction-Based Accelerators
Joseph Maheshe (University of British Columbia, BC); Guy G.F. Lemieux (University of British Columbia, BC)

SP-VF: Subspace-Preserving Vector Fitting for Scalable Multi-Port S-Parameter Modeling
Sijing Yang (Fudan University, China); Zhengyi Zhang (Fudan University, China); Lingli Wang (Fudan University, China)