2nd Sept 2026 (day 1)
| Time | Title / Description |
| 14:00-16:00 | AIxSIM Project Tutorial |
| 16:00-16:30 | Break |
| 16:30-18:00 | Invited Panel: ASAP Advances – the Last 40 Years |
3rd Sept 2026 (day 2)
| Time | Title / Description |
| 09:00-10:00 | Keynote 1: Subhasish Mitra, Stanford University |
| 10:00-11:00 | Session A: Best Paper Session A-1: Cutting DRAM Refresh Energy with Bank-Granular Rowhammer Mitigation Jeeho Ryoo (Fairleigh Dickinson University); Patrick Stockton (The University of Texas at San Antonio); Cory Davis (University of Texas at San Antonio); Marco Ho (British Columbia Institute of Technology); Michael Hsiao (Virginia Tech); Eugene B. John (University of Texas at San Antonio) A-2: ParaYosys: Tail-Aware Partition-Based Parallel RTL Synthesis Zhengyi Zhang, Sijing Yang, Lingli Wang (Fudan University) A-3: MPTAC: Memory Controller Partitioning and Traffic-Aware Contention Control in GPUs Vahid Geraeinejad, Paul Delestrac (KTH Royal Institute of Technology); Javier Barrera (Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC)); Francisco J Cazorla (Barcelona Supercomputing Center (BSC)); Masoumeh (Azin) Ebrahimi (KTH Royal Institute of Technology); Ahmed Hemani (Professor, KTH Royal Institute of Technology) |
| 11:00-11:30 | Break |
| 11:30-12:30 | Session B: Custom Instruction-Set and Vector Accelerators B-1: High-throughput interleaved QRD for FPGAs Bogdan Pasca, Yohann Uguen, Martin Langhammer (Altera) B-2: Real-Time MIMO MMSE Equalization Using Standard RISC-V Vector Extensions Zexu Tan, Sheikh Faizan Qureshi, Emil Matúš (Vodafone Chair); Pieter van der Wolf, Dmitry Ulyansky (Synopsys, Inc.); Gerhard Paul Fettweis (Vodafone Chair, CeTI, Barkhausen Institut) B-3: CIA: Composable Instruction-based Accelerators Brandon Freiberger (University of British Columbia); Jan Gray (Gray Research LLC); Guy Lemieux (University of British Columbia) |
| 12:30-14:00 | Lunch + Posters I |
| 14:00-15:00 | Keynote 2: Amir Yazdanbakhsh, Google DeepMind The Architect and the Agent: Searching for the AlphaZero of System Design Amir Yazdanbakhsh is a Research Scientist at Google DeepMind, where his work bridges the critical intersection of machine learning and computer architecture. |
| 15:00-15:45 | Session C: FPGA Design Automation Frameworks C-1: A Synthetic Benchmark Generator for Evaluating FPGA Incremental Tools Elmira Nezamfar, Steve Wilton (University of British Columbia) C-2: FQTree: Quantized Hardware Generation for Boosted Decision Trees Zhiqiang Que (University of Bristol); Chang Sun, Haiyang Wang (California Institute of Technology); Dinesh Pamunuwa, Roshan Weerasekera, Qijia Tang (University of Bristol); Bakhtiar Zadeh, Wayne Luk (Imperial College London); Maria Spiropulu (Caltech) C-3: RH+: Row-Hit Optimized Scheduling for PIM-based LLM Inference (short paper) Yongchan Jung (Fairleigh Dickinson University); Shafayat Mowla An, Byeong Kil Lee (University of Colorado at Colorado Springs); Jeeho Ryoo (Fairleigh Dickinson University) |
| 15:45-16:40 | Break + Posters II |
| 16:40-17:40 | Keynote 3: Tobias Becker, NVIDIA The Hardware of Intelligence: Application Specific Architectures for Next-Gen Agentic AI Tobias Becker is a Director in the NVIDIA LPU hardware team where he leads forward-looking explorations into new applications and accelerator architectures. |
| 18:30-20:00 | Conference Dinner |
4th Sept 2026 (day 3)
| Time | Title / Description |
| 09:00-10:00 | Keynote 4: Tulika Mitra, National University of Singapore |
| 10:00-11:00 | Session D: Emerging and Unconventional Applications D-1: SCU: An SFQ Co-Design for Bit-Vector Approximate Matching in Genome Alignment Peiyao Qu (State Key Lab of Processors, Institute of Computing Technology, CAS, China); Haihang You (SKL Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China); GuangMing Tang (Institute of Computing Technology, Chinese Academy of Sciences) D-2: Efficient Circuit Management and Scheduling in Multi-Node Quantum Systems with Dynamic Links Zefan Du (Fordham University); Wenrui Zhang (New Jersey Institute of Technology); Jake Gesseck, Wenqi Wei, Juntao Chen (Fordham University); Tao Han (New Jersey Institute of Technology); Zhiding Liang (Rensselaer Polytechnic Institute); Ying Mao (Fordham University) D-3: Ouros: A Dataflow-Driven Processor for Lazy Functional Languages Yukang Xie, Craig Ramsay, Robert Stewart, Hans-Wolfgang Loidl (Heriot-Watt University) |
| 11:00-11:30 | Break |
| 11:30-12:30 | Session E: Reconfigurable Processor Arrays and Approximate Computing E-1: Zero-Overhead Loop Control for Tightly Coupled Processor Arrays (TCPAs) Dominik Walter (Friedrich-Alexander-Universität Erlangen-Nürnberg); Frank Hannig (Friedrich-Alexander-Universität Erlangen-Nürnberg); Jürgen Teich (Friedrich-Alexander-Universität Erlangen-Nürnberg E-2: Symbolic Energy Analysis for Nested Loop Accelerators Avinash Mahesh Nirmala, Dominik Walter, Frank Hannig, Jürgen Teich (Friedrich-Alexander-Universität Erlangen-Nürnberg) E-3: VAHANA: Hardware-Aware Noise Addition Against Gradient Inversion Attacks Arsalan Ali Malik, Digvijay Anand, Chau-Wai Wong, Aydin Aysu (North Carolina State University) |
| 12:30-12:40 | Preview of ASAP 2027 |
| 12:40-14:00 | Lunch + Posters III |
| 14:00-15:00 | Session F: Reliable and Efficient Reconfigurable Computing F-1: FT-CGRA: Compiler-Transparent Fault Tolerance for CGRAs Ensieh Aliagha, Vijaya Shangamesh Manoharan Amutha, Diana Goehringer (TU Dresden) F-2: PASTE: A Physical-Aware Surrogate for FPGA Pre-Routing Timing Estimation Yunfei Dai, Kaixiang Zhu, Mingyang Chen, Lingli Wang (Fudan University) F-3: ADAD: An Energy-Efficient Hardware Solution for Real-Time Anomaly Detection Using Extended Decorrelation-Based Method Amirhossein Sadough, Mahyar Shahsavari (Radboud University); Mark Wijtvliet (Center of Competence, ASMPT); Marcel van Gerven (Radboud University) |
| 15:00-16:30 | Invited Panel: ASAP in 2066 |
| 16:30-16:45 | Break |
| 16:45-17:05 | Session G: Short Papers G-1: QXL – A Scalable Hardware Framework for Tabular Q-learning Inference on RISC-V Chinmay Krishna R (International Institute of Information Technology Bangalore); Pruthvi Parate, Phani Pavan Kambhampati (MS Research Student, VLSI and Embedded Systems, IIIT Bangalore); Madhav Rao (IIIT Bangalore) G-2: Towards Efficient Matrix Operations on CGRAs with Linear Computation Coding Dataflows Florian Rokohl, Alexander Lehnert, Marc Reichenbach (Institute of Applied Microelectronics and Computer Engineering, University of Rostock) G-3: When Timing is Uncertain, Infer: Probabilistic Early FPGA Timing Analysis for Robust Critical Path Optimization Omar Sharif, Filip Wojcicki, Tarik Ourida, Wayne Luk (Imperial College London); Christos-Savvas Bouganis (Imperial College London, UK) G-4: BenDi: An Energy-Efficient Quasi-Stochastic Systolic Architecture for Edge Bioelectronics Bochen Ye, Yihan Pan, Shady Agwa, Themis Prodromakis (University of Edinburgh) |
| 17:05-17:25 | Awards and Closing Remarks |